This invention most generally relates to operatively coupling materials having mismatched coefficients of thermal expansion, and more particularly, to minimizing stress induced by temperature changes in an integrated circuit or other such assemblies.
Focal plane arrays (FPA) are infrared detection systems that generally include an infrared detector array mounted on an integrated circuit. The detector array includes a number of photodetectors that have a sensitivity to the target range of infrared wavelengths to be monitored. The integrated circuit includes circuitry for receiving and processing signals detected by the detector array. Conventional interconnects or xe2x80x9cbump-bondingxe2x80x9d techniques are typically used to electrically and mechanically connect the detector array to the integrated circuit. Indium bumps are often used.
To ensure optimal detection performance, FPA assemblies are operated at cryogenic temperatures. To achieve such a performance environment, an FPA is typically mounted in a Dewar-type flask. A Dewar flask includes an inner flask and an outer flask separated from one another by a vacuum to prevent thermal transfer. The inner flask is cryogenically cooled. The FPA assembly is mounted in thermal contact with a surface of the inner flask thereby allowing the detector to operate at cryogenic temperatures.
A general problem with FPA technology involves differences in the coefficient of thermal expansion between the integrated circuit of the detector array and the surface of the inner flask. In particular, considerable stress is brought to bear on the assembly due to thermal mismatch between these layers. As the FPA is cycled between cold and ambient temperatures, the thermal mismatch related stress manifests on the connection points and circuitry thereby causing reliability issues, such as degraded performance, malfunction, and physical damage. Moreover, the larger the FPA assembly, the greater the degree of thermal-related stress that manifests.
Ideally, the coefficient of thermal expansion of the involved layers or surfaces should match so that they react to the temperature fluctuations similarly, minimizing the distortion of one material relative to another. However, other FPA properties required for proper function may dictate the use of materials having mismatched coefficients of thermal expansion.
A technique for minimizing the negative effects of mismatched coefficients of thermal expansion includes depositing thin layers of materials having spaced coefficients of thermal expansion so as to gradually transition from one coefficient of the desired materials to the other. However, this multilayer process increases manufacturing complexity, and is typically associated with a high failure rate.
In addition, many stacked layers may be required to ensure that the top layer remains flat and stress free. This stacking of layers increases the thermal mass of the assembly, as well as possible unevenness of the layers. Increased thermal mass increases temperature transition time, while uneven layers can cause uneven contractions during temperature transition. Uneven contractions contribute to undesired stress. Moreover, some of the layers cannot be made thin further contributing to unevenness.
What is needed, therefore, are techniques for compensating for mismatched coefficients of thermal expansion, while minimizing the thermal mass of the assembly.
One embodiment of the present invention provides a focal plane array assembly. The assembly includes a thermal interface board having first and second surfaces, wherein a flexible comb-like pattern adapted to compensate for a mismatch in coefficients of thermal expansion is formed in at least one of the first and second surfaces. A cryogenic cold finger having a metal surface that is operatively coupled to the first surface of the thermal interface board. The metal surface is associated with a first coefficient of thermal expansion. A signal processing board associated with a second coefficient of thermal expansion has one of its surfaces operatively coupled to the second surface of the thermal interface board. In one such embodiment, the thermal interface board is a single wafer (e.g., Silicon), and the flexible comb-like pattern includes a number of one dimensional or multi-dimensional (e.g., X and Y) cuts in a surface of the wafer. Alternatively, the thermal interface board includes a platform, and the flexible comb-like pattern includes a number of flexible bumps (e.g., Indium) on a surface of the platform.
Another embodiment of the present invention provides a method of manufacturing an integrated circuit assembly, such as a focal plane array or processor assembly. The method includes forming a flexible comb-like pattern adapted to compensate for a mismatch in coefficients of thermal expansion in at least one of first and second surfaces of a thermal interface board. The method further includes bonding the first surface of the thermal interface board to a surface of a temperature changing interface (e.g., cryogenic cold finger) associated with a first coefficient of thermal expansion. The method further includes bonding the second surface of the thermal interface board to a signal processing board (e.g., multiplexer of a detector array or a microprocessor) associated with a second coefficient of thermal expansion. Note that the bonding steps can be performed in any order. In one such embodiment, the thermal interface board is a single wafer (e.g., Silicon), and forming the flexible comb-like pattern includes providing a number of one dimensional or multi-dimensional (e.g., X and Y) cuts in a surface of the wafer thereby defining the flexible comb-like pattern in the surface of the thermal interface board. Alternatively, the thermal interface board includes a platform, and forming the flexible comb-like pattern includes providing a number of bumps (e.g., Indium) on a surface of the platform thereby defining the flexible comb-like pattern in the surface of the thermal interface board.
Another embodiment of the present invention provides an integrated circuit assembly. The assembly includes a thermal interface board having first and second surfaces, wherein a flexible comb-like pattern adapted to compensate for a mismatch in coefficients of thermal expansion/contraction is formed in at least one of the first and second surfaces. A temperature changing interface (e.g., Dewar flask type) associated with a first coefficient of thermal expansion/contraction is operatively coupled to the first surface of the thermal interface board. A signal processing board (e.g., multiplexer of a detector array or a microprocessor) associated with a second coefficient of thermal expansion/contraction is operatively coupled to the second surface of the thermal interface board. In one such embodiment, the thermal interface board is a single wafer (e.g., Silicon), and the flexible comb-like pattern includes a number of one dimensional or multi-dimensional (e.g., X and Y) cuts in a surface of the wafer. Alternatively, the thermal interface board includes a platform, and the flexible comb-like pattern includes a number of bumps (e.g., Indium) on a surface of the platform.
Note that the xe2x80x9ccoefficient of thermal expansionxe2x80x9d as used herein is intended to represent the coefficient of thermal contraction as well. Generally stated, stress related to thermal expansions and/or contractions can be compensated for by employing embodiments of the present invention.